1. Field of the Disclosure
Embodiments of the invention relate to chemical/mechanical polishing (CMP) processes, such as those adapted for use in the fabrication of microelectronic devices. More particularly, embodiments of the invention relate to CMP processes yielding material layers having reduced thickness variations.
2. Description of the Related Art
As microelectronic devices, such as those formed on semiconductor substrates, become ever more densely integrated, the material layer planarization processes used to fabricate such devices become more and more critical. That is, since highly integrated semiconductor devices typically include stacked material layers and related interconnections, the upper surface flatness and regular thickness of a material layer are critical design parameters. Any unevenness or irregularity (e.g., non-uniform thickness and/or non-planar surface condition) of the substrate or an intermediate material layer presents a variety of problems which are well-documented in the art.
Accordingly, planarization processes are applied at various stages within the sequence of fabrication processes used to manufacture semiconductor devices. Planarization processes are used to minimize irregularities and thickness variations in a substrate layer or an intermediate material layer. (Hereafter, either the actual surface of a substrate material, and/or the surface of one or more material layers formed on the substrate being subjected to planarization will be generally referred to as “the working surface”).
One common planarization technique is known as chemical/mechanical polishing (CMP). In CMP, a working surface is pressed against a rotating polishing pad. An abrasive and/or a chemically reactive solution known as a “slurry” is then introduced onto the polishing pad. The mechanical effect of the pressure applied through the polishing pad and the chemical reaction resulting from of introduction of the slurry selectively remove material from the working surface and produce a more uniform material layer.
Once a working surface has been polished using a CMP process, it may be used as a substrate (i.e., an underlying layer) for another material layer. In this manner, contemporary semiconductor devices are formed from multiple stacked material layers.
A difficulty commonly encountered during CMP processing is one in which different rates of polishing (i.e., the respective rates of material removal) arise for different materials forming a working surface. Additionally, different polishing rates may be encountered for different regions of the working surface, regardless of their relative material composition. Thus, care must be taken to avoid over-polishing, under-polishing, or uneven polishing within disparate regions of a working surface or across disparate materials forming the working surface.
For example, one common form of selective over-polishing results in a so-called “dishing effect.” FIGS. 1A and 1B depict a portion of an exemplary working surface of a semiconductor substrate A10. Working surface A10 includes an area of dense element formation and an area of less dense (e.g., wide open) element formation on a substrate material layer A12. Selected portions of substrate material A12 have been previously removed to form, for example, trench structure A22 and well structures A18 and A20. A material layer A16, such as an interlayer dielectric (ILD), is then formed to substantially cover substrate material layer A12 and to fill trench structure A22 and well structures A18 and A20.
ILD layer A16 may be formed of multiple layers, but is commonly formed to insulate other material layers such as insulation layer A24 and patterned conductive layer A14 formed on substrate material layer A12. As formed over all of these intervening material layers and associated elements, the upper surface of ILD layer A16 is significantly uneven. Such unevenness prevents the practical formation of additional material layers or components on the upper surface of ILD layer A16. Thus, a planarization (e.g., a CMP) process is commonly applied to working surface A10 to planarize ILD layer A16.
Unfortunately, the disparate natures of the wide open area and the dense area, as well as the different material compositions of ILD layer A16 and conductive layer A14 make even planarization very difficult to achieve. As shown in FIG. 1B, for example, the portion of ILD layer A16 overlaying the wide open area is commonly over-polished relative to the remainder of working surface A10. The dish shaped over-polishing defect A26 formed in working surface A10 potentially may subsequently result in the faulty formation of an overlying material layer.
FIGS. 1C and 1D illustrate two possible fabrication defects associated with uneven polishing of a working surface. FIGS. 1C and 1D illustrate different regions of a substrate in which an ILD layer A16 has been formed with an uneven thickness (e.g., difference A21) as between the two regions. Because ILD layer A16 is relatively thick in the region of FIG. 1C, an under-etching of related material layer results in a partial contact failure between connection element A23 and an underlying conductive region of the substrate. In contrast, the relatively thin nature of ILD layer A16 in the region of FIG. 1D results in an over-etching of the related material and punch-through by connection element A23.
While a considerable number of approaches have been developed to abate such polishing defects, most of these approaches suffer from a number of their own problems, such as unpredictable performance, lengthy processing times, inefficient and costly procedures, etc. For example, U.S. Pat. No. 5,385,866 describes a CMP process that uses a barrier film made of nitride disposed over a special polish stop layer formed from boron nitride (or oxidized boron nitride). The polish stop layer, in turn, is disposed atop a number of transistor gates. While the barrier film is used to protect the transistor gates, the planarization process must cut through the barrier film to reach the polish stop layer before planarization is considered complete. While the polish stop layer appears to provide an adequate hard stop over each transistor gate, the different removal rates between the polish stop layer and an insulating layer disposed over the barrier film and polish stop layer may be improved. However, this approach to CMP provides only a mediocre rate of material removal and fails to adequately address the problem of dishing in substrates having both relatively dense and sparsely populated regions.
Published United States Patent Application No. 2004/0127045 describes a CMP process wherein nano-sized abrasive particles are added to a slurry to increase the rate of polishing. Further, U.S. Pat. No. 6,914,001 to Lee et al. describes a CMP process wherein both nano-sized abrasive particles and one or more passivation agents are added to a slurry to increase the rate of material removal and provide removal selectivity between different material layers. However, as before, these conventional approaches do not address the problem of dishing in substrates having both relatively dense and sparsely populated regions.
Indeed, the requirement for a highly effective and efficiently applied CMP process adapted planarize the working surface of a material layer formed on a substrate having densely filled and wide open regions remains unmet. Current approaches still result in either very slow CMP processing times, uncontrolled and unpredictable results, and polishing defects, such as the dishing effect.